The dimensions of via diameters are generally same on a same chip irrespective of locations of the vias. Accordingly, when the via diameter is large in the entire chip, an eFuse is more susceptible to initial cutting defect and re-coupling. When the via diameter is large, there is a possibility that a resistance balance between a metal interconnection and a via can not be taken so that stress at the time of cutting is not applied to the bottom of the via but to on the metal interconnection. If the cutting stress is applied to any positions other than the via bottom, the cross sectional shape at the time of cutting becomes complicated to cause the initial cutting defect and re-coupling defect.
On the contrary, if the via diameter is small in the entire chip, the via is not sufficiently filled and there is a risk that quality degradation such as connection failure may occur.
In conjunction with the above description, Japanese Patent Publication (JP 2007-305693A: Patent Literature 1) discloses a semiconductor device. In this technique, the eFuse includes an upper layer interconnection, a via connected to the upper interconnection and a lower layer interconnection connected to the via. An outflow portion is formed to allow an outflow of a conductor from the upper layer interconnection to the outside and a gap portion is formed between the lower layer interconnection and the via.
In an existing semiconductor device using an eFuse (electric fuse), the via diameter is sometimes made large and the interconnection is made thin. In such a case, if a resistance balance cannot be taken, there is a possibility that a initial cutting defect or re-coupling defect occurs.
It could be considered that it is effective to make the via diameter small or make the interconnection thick, in order to keep the resistance balance. However, in the former case, via quality would be degraded if the via diameter is uniformly reduced in the entire chip. Also, in the latter case, if the interconnection is made thick, it would be difficult to realize a layout because an area for interconnections increases.